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sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan ordering number : enn7713 40804tn (ot) no.7713-1/15 overview the lc74986nwf and LC74986NWV are video signal processing ics that perform resolution conversion, interlaced to progressive scan (ip) conversion, and image quality improvement without requiring the use of external field (frame) memory. these ics can display a wide variety of video signals and formats on a flat panel display. these ics also provide image quality improvement and adjustment functions to create the optimal image quality for the flat panel display used. they also include an osd function that displays characters with the sizes optimal for the size of panel used. a flat panel tv monitor with the necessary video signal processing circuits can be formed easily by combining one of these ics with a video decoder, a/d converters, a microcontroller, and an lcd panel. features ? multi-source support ntsc, pal, and dtv (480i and 480p) inputs progressive scan inputs up to xga (the LC74986NWV supports up to svga.) supports both rgb and ycbcr (4:4:4 24 bits, 4:2:2 16 bits or 8 bits) inputs (built-in ycbcr to rgb converter). ? resolution conversion independent horizontal and vertical expansion and reduction in the horizontal direction interlaced to progressive scan conversion ? image quality correction sharpness, color, tint, white/black stretch, brightness, contrast, white balance, black balance built-in lookup table based gamma correction circuit (common characteristics for each 8-bit rgb value can be programmed.) ? panel interface single rgb 24-bit or 18-bit, or dual rgb 48-bit or 36-bit signal output (built-in dither processing) horizontal sync signal, vertical sync signal, data enable signal, and pixel clock outputs ? other features no external frame memory required (the input and output have the same frame period.) built-in osd function (510 characters, 8 colors, built-in 8-character font ram) i 2 c bus interface (the osd function can also be controlled over a 3-wire bus.) low-power design ic specifications ? supply voltage: i/o: 3.3v, core: 2.5v (lc74986nwf) or 1.8v (LC74986NWV) dual power supply system ? maximum operating frequency: 85mhz (lc74986nwf), 40mhz (LC74986NWV) ? package: 144-pin sqfp sanyo semiconductors data sheet lc74986nwf LC74986NWV cmos ic lcd tv scan converter ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein.
no.7713- 2 /15 lc74986nwf , 74986nwv applications ? lcd tvs and lcd monitors ? car tvs and car monitors ? pdp tvs specifications absolute maximum ratings at ta = 25 c, dv ss = 0v, av ss = 0v. values in parentheses apply to the LC74986NWV. these are provisional specifications for the lc74986nwf. parameter symbol conditions ratings unit maximum supply voltage v dd 1 C0.3 to +3.6 v v dd 2 C0.3 to +4.6 v input voltage v i C0.3 to v dd 2+0.3 v output voltage v o C0.3 to v dd 2+0.3 v allowable power dissipation pd max tbd (0.6) w storage temperature tstg C55 to +125 c operating temperature topr C30 to +70 c allowable operating ranges at ta = C30 to +70 c. values in parentheses apply to the LC74986NWV. these are provisional specifications for the lc74986nwf. * : certain input pins have built-in pull-down resistors. thus there are cases where, due to the circuit structure, the quiescent c urrent characteristics cannot be guaranteed. parameter symbol conditions ratings unit min typ max supply voltage v dd 1 dv dd 1 2.3 (1.7) 2.5 (1.8) 2.7 (1.9) v v dd 2 dv dd 2, av dd 3.0 3.3 3.6 v input voltage range v in 0 3.6 v dc characteristics at v dd 1 = 2.5v (lc74986nwf) or 1.8v (LC74986NWV), v dd 2 = 3.3v, ta = C30 to +70 c. these are provisional specifications for the lc74986nwf. parameter symbol conditions ratings unit min typ max input high-level voltage v ih cmos level inputs 0.7v dd 2 v cmos level schmitt inputs 0.75v dd 2 v input low-level voltage v il cmos level inputs 0.2v dd 2 v cmos level schmitt inputs 0.15v dd 2 v input high-level current i ih v i =v dd 2 C10 +10 a v i = v dd 2, with a pull-down resistor used +10 +100 a input low-level current i il v i =v ss C10 +10 a b4 type, i oh =C2ma v dd 2C0.4 v output high-level voltage v oh b8 type, i oh =C4ma v dd 2C0.4 v b12 type, i oh =C6ma v dd 2C0.4 v b4 type, i ol =2ma 0.4 v output low-level voltage v ol b8 type, i ol =4ma 0.4 v b12 type, i ol =6ma 0.4 v output leakage current i oz in high-impedance output mode C10 +10 a pull-down resistance r dn 126 k quiescent current i dd 1 outputs open, vi=v ss or v dd 1 300 a quiescent current* i dd 2 outputs open, vi=v ss or v dd 2 10 a
no.7713- 3 /15 lc74986nwf , 74986nwv 20.0 22.0 20.0 22.0 0.145 0.2 0.5 (1.25) 0.5 1 36 37 72 73 108 109 144 (1.4) 1.6max 0.1 package dimensions unit : mm 3214 sanyo : sqfp144 input and output signals ? input signals items shown in parentheses are alternate functions that can be selected by setting a register. signal type number of pins symbol description notes ? 24-bit rgb ? 24-bit ycbcr, 16-bit or 8-bit 4:2:2 video signals 8 vpa1 input port a ? the input polarity is arbitrary. the ic discriminates the polarity automatically. ? the input polarity is arbitrary. the ic discriminates the polarity automatically. ? the input polarity is arbitrary. the ic discriminates the polarity automatically. ? the pin can be selected by setting an internal register. sync signals hsi vsi vpbh vpbv (aics/pdown2) 8 vpa2 8 vpa3 8 vpb1 (rout_2) input port b (external video or dual output) port a system horizontal sync signal port a system vertical sync signal port b system horizontal sync signal port b system vertical sync signal (three-wire bus chip select, power down) 8 vpb2 (gout_2) 8 vpb3 (bout_2) 1 ? the input polarity is arbitrary. it can be inverted internally. ? devi must be held fixed at 1 when a composite video signal is input. data enable signals dehi port a system horizontal data enable, port a system composite enable 1 1 1 1 ? the input polarity is arbitrary. it can be inverted internally. devi port a system vertical data enable 1 ? only h/v composite signals are supported. ? the input polarity is arbitrary. it can be inverted internally. vpbden (vpben) port b system composite data enable (external video enable) 1 continued on next page.
no.7713- 4 /15 lc74986nwf , 74986nwv continued from preceding page. signal type number of pins symbol description notes ? max85mhz(lc74986nwf), max40mhz(LC74986NWV) pixel clock clock enable 1 clki port a system clock ? max85mhz(lc74986nwf), max40mhz(LC74986NWV) 1 dclki display clock ? max85mhz(lc74986nwf), max40mhz(LC74986NWV) 1 vpbck port b system clock ? positive logic 1 clkien port a system clock enable fixed oscillator ? max85mhz(lc74986nwf), max40mhz(LC74986NWV) 1 xtal used for the control bus and various detection functions system reset ? inverted logic 1 rst system reset external video ? inputs a video signal synchronized with the output ? dither processing possible. image quality adjustments not possible. ? 6-bit input also possible ? positive logic 8 vpb1 8 vpb2 8 vpb3 1 vpben (vpbden) external video signal (input port b, dual output) external video signal enable (port b system composite data enable) ? output signals signal type number of pins symbol description notes ? dithered 6-bit output also possible ? dual output also possible. (odd/even inversion possible) ? first data ? dedicated dual system output. (odd/even inversion possible) ? second data ? the sync signal, position, and polarity can be set. ? the polarity can be set. ? the polarity can be set. video signals sync signals data enable signals pixel clocks clamp pulse 8 rout r 8 gout g 8 bout b 8 rout_2 (vpb1) 8 gout_2 (vpb2) 8 bout_2 (vpb3) 1 1 1 1 hso vso deho devo dual output (input port b, external video signal) horizontal sync signal vertical sync signal, composite signal horizontal data enable vertical data enable, composite enable ? the polarity can be inverted. 1 clkio outputs the input clock ? the polarity can be inverted. divided-by-two output possible in dual output mode. 1 dclko display clock ? output at the clamp position. the position can be changed. the pulse width can be changed. 1 clpp used for a/d conversion clamp levels divided output signal for external pll circuit ? clamp level discrimination output (too large: low, too small: high, match: high impedance) 1 clpvpa1 vp1 clamp level 1 clpvpa2 vp2 clamp level 1 clpvpa3 vp3 clamp level 1 pllhio for an external pll circuit
no.7713- 5 /15 lc74986nwf , 74986nwv ? control signals signal type number of pins symbol description notes ? for osd control (normally, the i 2 c bus is used.) ? used for setting internal registers and for internal status output. ? the slave address is 0111000 + (r/w) ? osd control, gamma correction control ? normally low. 0111000 + (r/w) ? switches the ic to 0111001 + (r/w) when high. three-wire bus signals i 2 c bus signals 1 aics (vpbv) 1 aida three-wire bus chip select (port b system vertical sync signal) data bus 1 aick bus clock 1 sda data bus 1 scl bus clock 1 i 2 csel slave switching ? other signals signal type number of pins symbol description notes ? the output can be forcibly muted from this pin. inverted logic forcible mute signal 1 mute muting ? low-power mode used when the ic is not operating. this pin is normally held at the high level. power down (low- power mode) signal 2 pdown1 pdown2 (vpbv) low-power mode (port b system vertical sync signal) ? used for test settings. this pin must be held at the low level during normal operation. test signals 1 scanen test ? used for test settings. this pin must be held at the low level during normal operation. 1 scanmod test ? used for test settings. this pin must be held at the low level during normal operation. 5 test test
no.7713- 6 /15 lc74986nwf , 74986nwv pin assignments dv ss pllhio clkio clkien clki av dd av ss vcocnt1 vcorng1 pdo 1 dv dd 1 dv ss sd a scl i 2 csel mute aics (vpbv) aid a aic k rst pdo w n1 pdo w n2 (vpbv) dv dd 1 dv ss xt al dclki dv dd 1 dv ss dv ss dv ss vpbc k dv dd 1 dv ss dclko vpbh dv dd 1 dv ss vp a17 vp a16 vp a15 vp a14 vp a13 vp a12 vp a1 1 vp a10 vp a27 vp a26 vp a25 vp a24 vp a23 vp a22 vp a21 vp a20 dv dd 2 dv ss vp a37 vp a36 vp a35 vp a34 vp a33 vp a32 vp a31 vp a30 clpvp a1 clpvp a2 clpvp a3 clpp vsi hsi devi dehi dv dd 2 dv dd 2 bo ut7 bo ut6 bo ut5 bo ut4 bo ut3 bo ut2 bo ut1 bo ut0 dv ss dv dd 2 gout7 gout6 gout5 gout4 gout3 gout2 gout1 gout0 dv ss dv dd 2 rout7 rout6 rout5 rout4 rout3 rout2 rout1 rout0 dv ss dv dd 2 vso hso devo deho dv ss dv dd 1 vpb30 (bout0_2) vpb31 (bout1_2) vpb32 (bout2_2) vpb33 (bout3_2) vpb34 (bout4_2) vpb35 (bout5_2) vpb36 (bout6_2) vpb37 (bout7_2) vpb20 (gout0_2) vpb21 (gout1_2) vpb22 (gout2_2) vpb23 (gout3_2) vpb24 (gout4_2) vpb25 (gout5_2) vpb26 (gout6_2) vpb27 (gout7_2) dv ss dv dd 1 vpb10 (rout0_2) vpb1 1 (rout1_2) vpb12 (rout2_2) vpb13 (rout3_2) vpb14 (rout4_2) vpb15 (rout5_2) vpb16 (rout6_2) vpb17 (rout7_2) vpben (vpbden) test4 test3 test2 test1 test0 scanmo d scanen dv ss 109 110 115 120 125 130 135 140 144 108 105 100 95 90 85 80 75 73 1 5 10 15 20 25 30 35 36 72 70 65 60 55 50 45 40 37 lc74986nwf LC74986NWV top view
no.7713- 7 /15 lc74986nwf , 74986nwv pin symbol i/o and type function notes number i/o type 1 dv ss p digital system ground 2 pllhio o gqcio19 input or external pll divided clock output the divider ratio can be set over the i 2 c bus. 3 clkio o gqcio20 outputs the input clock has the same period as the input system. the output can be inverted by a setting controllable over the i 2 c bus. 4 clkien i gqcio02 port a system input clock enable this input is normally held fixed at the high level. (positive logic.) 5 clki i gqcio02 port a system input clock input signal pixel clock 6 av dd p analog system power supply: 3.3v connect to dv dd 2 if unused. 7 av ss p analog system ground 8 vcocnt1 i gqcio10 pll vco control voltage input connect to av ss if unused. 9 vcorng1 i gqcio10 pll range setting resistor connection connect to av ss if unused. 10 pdo1 o gqcio09 pll phase comparator output leave open if unused. 11 dv dd 1 p digital system power supply: 2.5v (1.8v) 12 dv ss p digital system ground 13 sda b gqcio22 i 2 c bus data used for setting internal registers and for reading out ic status. 14 scl i gqcio03 i 2 c bus clock also used for osd control and gamma correction settings. 15 i 2 csel i gqcio18 i 2 c bus slave address switching normally left open (slave address: 70h) or connected to dv ss . 16 mute i gqcio02 muting control inverted logic 17 aics (vpbv) i gqcio03 chip select or port b system vertical sync three-wire bus: use is optional. signal only used for osd control (normally, the i 2 c bus is used.) 18 aida i gqcio03 data the aics pin uses inverted logic. 19 aick i gqcio03 clock vpbp can be used by setting a register. 20 rst i gqcio03 initial reset inverted logic 21 pdown1 i gqcio02 power down normally held fixed at the high level (used for testing.) 22 pdown2 (vpbv) i gqcio03 power down or port b system vertical sync (used for testing.) vpbv can be used by setting a register. signal 23 dv dd 1 p digital system power supply: 2.5v (1.8v) 24 dv ss p digital system ground 25 xtal i gqcio02 clock input for the detection functions connection for the fixed-frequency oscillator 26 dclki i gqcio02 display clock input display processing pixel clock 27 dv dd 1 p digital system power supply: 2.5v (1.8v) 28 dv ss p digital system ground 29 dv ss p digital system ground 30 dv ss p digital system ground 31 vpbck i gqcio02 port b system input clock port b system input signal pixel clock 32 dv dd 1 p digital system power supply: 2.5v (1.8v) 33 dv ss p digital system ground 34 dclk0 o gqcio20 lcd panel module clock output has the same period as dclki. alternatively, may have 1/2 the period. 35 vpbh i gqcio03 port b system horizontal sync signal port b system input horizontal sync signal 36 dv dd 1 p digital system power supply: 2.5v (1.8v) 37 dv ss p digital system ground 38 deho o gqcio19 fpd module horizontal enable the polarity can be selected over the i 2 c bus. 39 devo o gqcio19 fpd module vertical enable a composite signal can be output from devo. 40 hso o gqcio19 fpd module horizontal sync signal the polarity and pulse width can be set over the i 2 c bus. 41 vso o gqcio19 fpd module vertical sync signal a composite sync signal can be output from vso. 42 dv dd 2 p digital system power supply: 3.3v 43 dv ss p digital system ground 44 rout0 o gqcio19 fpd module r output lsb 45 rout1 o gqcio19 (the rout5:0 pins are used for 6-bit output.) 46 rout2 o gqcio19 when 2-phase output is used, the first byte is data. 47 rout3 o gqcio19 (msb when 6-bit output is selected) 48 rout4 o gqcio19 49 rout5 o gqcio19 50 rout6 o gqcio19 51 rout7 o gqcio19 msb 52 dv dd 2 p digital system power supply: 3.3v 53 dv ss p digital system ground pin functions items in parentheses apply to the LC74986NWV. continued on next page.
no.7713- 8 /15 lc74986nwf , 74986nwv continued from preceding page. pin symbol i/o and type function notes number i/o type 54 gout0 o gqcio19 fpd module g output lsb 55 gout1 o gqcio19 (the rout5:0 pins are used for 6-bit output.) 56 gout2 o gqcio19 when 2-phase output is used, the first byte is data. 57 gout3 o gqcio19 (msb when 6-bit output is selected) 58 gout4 o gqcio19 59 gout5 o gqcio19 60 gout6 o gqcio19 61 gout7 o gqcio19 msb 62 dv dd 2 p digital system power supply: 3.3v 63 dv ss p digital system ground 64 bout0 o gqcio19 fpd module b output lsb 65 bout1 o gqcio19 (the rout5:0 pins are used for 6-bit output.) 66 bout2 o gqcio19 when 2-phase output is used, the first byte is data. 67 bout3 o gqcio19 (msb when 6-bit output is selected) 68 bout4 o gqcio19 69 gout5 o gqcio19 70 gout6 o gqcio19 71 gout7 o gqcio19 msb 72 dv dd 2 p digital system power supply: 3.3v 73 dv ss p digital system ground 74 scanen i gqcio18 test settings normally left open or connected to dv ss 75 scanmod i gqcio18 76 test0 i gqcio18 77 test1 i gqcio18 78 test2 i gqcio18 79 test3 i gqcio18 80 test4 i gqcio18 81 vpben (vpbden) i gqcio03 external video input enable or port b system enable: positive logic. connect to dv ss if unused. enable 82 vpb17 (rout7_2) i/o gqcio35 video data input (r) or port b system input msb 83 vpb16 (rout6_2) i/o gqcio35 or 2-phase output (msb when 6-bit input or output mode selected) 84 vpb15 (rout5_2) i/o gqcio35 (data is input to vpb15 to vpb10 in 6-bit input mode.) 85 vpb14 (rout4_2) i/o gqcio35 second data in 2-phase output mode 86 vpb13 (rout3_2) i/o gqcio35 connect to dv ss if unused. 87 vpb12 (rout2_2) i/o gqcio35 88 vpb11 (rout1_2) i/o gqcio35 89 vpb10 (rout0_2) i/o gqcio35 lsb 90 dv dd 1 p digital system power supply: 2.5v (1.8v) 91 dv ss p digital system ground 92 vpb27 (gout7_2) i/o gqcio35 video data input (g) or port b system input msb 93 vpb26 (gout6_2) i/o gqcio35 or 2-phase output (msb when 6-bit input or output mode selected) 94 vpb25 (gout5_2) i/o gqcio35 (data is input to vpb25 to vpb20 in 6-bit input mode.) 95 vpb24 (gout4_2) i/o gqcio35 second data in 2-phase output mode 96 vpb23 (gout3_2) i/o gqcio35 connect to dv ss if unused. 97 vpb22 (gout2_2) i/o gqcio35 98 vpb21 (gout1_2) i/o gqcio35 99 vpb20 (gout0_2) i/o gqcio35 lsb 100 vpb37 (bout7_2) i/o gqcio35 video data input (b) or port b system input msb 101 vpb36 (bout6_2) i/o gqcio35 or 2-phase output (msb when 6-bit input or output mode selected) 102 vpb35 (bout5_2) i/o gqcio35 (data is input to vpb35 to vpb30 in 6-bit input mode.) 103 vpb34 (bout4_2) i/o gqcio35 second data in 2-phase output mode 104 vpb33 (bout3_2) i/o gqcio35 connect to dv ss if unused. 105 vpb32 (bout2_2) i/o gqcio35 106 vpb31 (bout1_2) i/o gqcio35 107 vpb30 (bout0_2) i/o gqcio35 lsb 108 dv dd 1 p digital system power supply: 2.5v (1.8v) 109 dv ss p digital system ground continued on next page.
no.7713- 9 /15 lc74986nwf , 74986nwv continued from preceding page. pin symbol i/o and type function notes number i/o type 110 vpa17 i gqcio02 port a system input msb 111 vpa16 i gqcio02 y/r/ycbcr multiplexed 112 vpa15 i gqcio02 connect to dv ss if unused. 113 vpa14 i gqcio02 114 vpa13 i gqcio02 115 vpa12 i gqcio02 116 vpa11 i gqcio02 117 vpa10 i gqcio02 lsb 118 vpa27 i gqcio02 port a system input msb 119 vpa26 i gqcio02 cb/g/cbcr multiplexed or ycbcr multiplexed 120 vpa25 i gqcio02 connect to dv ss if unused. 121 vpa24 i gqcio02 122 vpa23 i gqcio02 123 vpa22 i gqcio02 124 vpa21 i gqcio02 125 vpa20 i gqcio02 lsb 126 dv dd 2 p digital system power supply: 3.3v 127 dv ss p digital system ground 128 vpa37 i gqcio02 port a system input msb 129 vpa36 i gqcio02 cr/b/ycbcr multiplexed 130 vpa35 i gqcio02 connect to dv ss if unused. 131 vpa34 i gqcio02 132 vpa33 i gqcio02 133 vpa32 i gqcio02 134 vpa31 i gqcio02 135 vpa30 i gqcio02 lsb 136 clpvpa1 o gqcio21 vpa1 clamp level detection output the clamp level can be set over the i 2 c bus. 137 clpvpa2 o gqcio21 vpa2 clamp level detection output 138 clpvpa3 o gqcio21 vpa3 clamp level detection output 139 clpp o gqcio05 clamp pulse output the clamp position and width can be set over the i 2 c bus. 140 vsi i gqcio03 vertical sync signal input arbitrary polarity. the ic discriminates the polarity 141 hsi i gqcio03 horizontal sync signal input automatically. 142 devi i gqcio03 vertical data enable input arbitrary polarity. a composite signal can be input to dehi. 143 dehi i gqcio03 horizontal data enable input hold devi fixed at the high level if a composite signal is used. 144 dv dd 2 p digital system power supply: 3.3v
no.7713- 10 /15 lc74986nwf , 74986nwv pin type input or output function equivalent circuit applicable pins circuit type gqcio02 input clkien, clki, xtal, dclki, pdown1, vpa10 to vpa17, vpa20 to vpa27, vpa30 to vpa37, mute, vpbck gqcio03 schmitt trigger input scl, aics, aida, aick, rst, vpben, vsi, hsi, devi, dehi, pdown2, vpbh gqcio18 input with built-in pull- down resistor i 2 csel, scanen, scamod, test0 to test4 * gqcio05 gqcio19 gqcio20 4ma drive output 8ma drive output 12ma drive output clpp * pllhio, deho, devo, hso, vso, rout0 to rout7, gout0 to gout7, bout0 to bout7 * clkio, dclko * gqcio21 4ma 3-state drive output clpvpa1, clpvpa2, clpvpa3 * gqcio22 open-drain i/o sda gqcio10 analog through vcocnt1, vcorng1 gqcio09 analog through pdo1 * gqcio35 8ma drive bidirectional vpb10 to vpb17, vpb20 to vpb27, vpb30 to vpb37 notes: ? pins marked with an asterisk ( * ) must be left open if unused. ? if noise or other problems due to external factors can be expected, input pins with built-in pull-down resistors must be conn ected to dv ss . ? all of the dv dd * and dv ss pins must be connected to the corresponding power supply system. these pins must not be left open. ? all of the av dd and av ss pins must be connected to the corresponding power supply system. these pins must not be left open.
no.7713- 11 /15 lc74986nwf , 74986nwv input and output data timing ? input data timing 1 t hi t lo t ck t su t hd clki input data v dd /2 v dd /2 pin name parameter symbol min max unit clock low level time t lo 5.5 (12.5) ns clki clock high level time t hi 5.5 (12.5) ns clock period t ck 11.0 (25.0) ns vpa1 [7:0], vpa2 [7:0] input data setup time t su 3.0 ns vpa3 [7:0], vsi, hsi, input data hold time t hd 3.0 ns devi, dehi, clkien items in parentheses refer to the LC74986NWV. * : an input clock duty of 50% is recommended. ? input data timing 2 t hi t lo t ck t su t hd dclki input data v dd /2 v dd /2 pin name parameter symbol min max unit clock low level time t lo 5.5 (12.5) ns dclki clock high level time t hi 5.5 (12.5) ns clock period t ck 11.0 (25.0) ns vpben, vpb1 [7:0], input data setup time t su 3.0 ns vpb2 [7:0], vpb3 [7:0] input data hold time t hd 3.0 ns items in parentheses refer to the LC74986NWV. * : an input clock duty of 50% is recommended.
no.7713- 12 /15 lc74986nwf , 74986nwv ? output data timing 1 t hi t lo t ck t su t hd clkio output data v dd /2 v dd /2 ? output data timing 2 t hi t lo t ck t su dclko output data v dd /2 v dd /2 t hd pin name parameter symbol min max unit clock low level time t lo 5.5 (12.5) ns clkio clock high level time t hi 5.5 (12.5) ns clock period t ck 11.0 (25.0) ns clpvpa1, clpvpa2, output data setup time t su 2.0 ns clpvpa3, clpp, pllhio output data hold time t hd 2.0 ns items in parentheses refer to the LC74986NWV. pin name parameter symbol min max unit clock low level time t lo 5.5 (12.5) ns dclko clock high level time t hi 5.5 (12.5) ns clock period t ck 11.0 (25.0) ns deho, devo, hso, output data setup time t su 2.0 ns vso, rout [7:0], output data hold time t hd 2.0 ns gout [7:0], bout [7:0] items in parentheses refer to the LC74986NWV.
no.7713- 13 /15 lc74986nwf , 74986nwv input and output clock timing ? input system clock timing input clki output clkio t hi t ck t lo t out v dd /2 v dd /2 pin name parameter symbol min max unit clock low level time t lo 5.5 (12.5) ns clki clock high level time t hi 5.5 (12.5) ns clock period t ck 11.0 (25.0) ns clkio clkio delay time t out 0 17 ns items in parentheses refer to the LC74986NWV. pin name parameter symbol min max unit clock low level time t lo 5.5 (12.5) ns dclki clock high level time t hi 5.5 (12.5) ns clock period t ck 11.0 (25.0) ns dclko dclko delay time t out 0 20 ns items in parentheses refer to the LC74986NWV. ? output system clock timing input dclki output dclko t hi t ck t lo t out1 v dd /2 v dd /2
no.7713- 14 /15 lc74986nwf , 74986nwv internal block diagram input processing vp a1[7:0] vp a2[7:0] vp a3 [ 7:0 ] 1 10 1 1 7 1 18 125 128 135 ycbcr rgb sharpness color tint scaling processing horizontal reduction horizontal and vertical enlargement rout[7:0] gout[7:0] bo ut [ 7:0 ] output processing 44 51 54 61 64 71 mix os d vsi 140 input timing hsi 141 devi 142 dehi 143 clki 5 clkien * 1, * 2: register selection 4 output timing vso 41 hso 40 devo 39 deho 38 dclko 34 dclki 26 a ics*2/aida/aick 17 18 19 13 14 sda/scl vpb1[7:0]*1 vpb2[7:0]*1 vpb3 [ 7:0 ] *1 82 89 92 99 100 107 vpben 81 xt al 25 b 8 g 8 r 8 c r cb y c r cb y 24 rgb ycbcr b g r data select white/black expansion white balance contrast black balance brightness gamma correction dithering ccd select external video rout_2[7:0]*1 guot _ 2[7:0]*1 bo ut _ 2 [ 7:0 ] *1 82 89 92 99 100 107 24 8 8 8 vpbh 35 vpbv*2 17 select 24 24 vpbck 31
ps no.7713- 15 /15 lc74986nwf , 74986nwv specifications of any and all sanyo products described or contained herein stipu late the performance , characteristics, and functions of the described products in the independent stat e, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's p roducts or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability product s. however, any and al l semiconductor products fail with some probability. it is possible that these pro babilistic failures coul d give rise to accidents or events that could endanger human lives, that could giv e rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt sa fety measures s o t hat these kinds of accidents or events cannot occur. such measures include but a re not limited to protectiv e circuits and error prevention circuits for safe design, redundant design, and st ructural design. in the event that any or all sanyo products(including technical data,services) d escribed o r contained herein are controlled under any of applicable local export control law s and regulations, such products m ust not be e xpor ted without obtaining the e xpor t license from the author ities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by a ny means, electronic o r mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co. , ltd. any and all information described or contained herein are subject to change with out notice due to product/technology improvement, etc. when designing equipment, refer to the "del ivery specification " for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for ex ample only ; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of inte llectual property rights or other rights of third parties. this catalog provides information as of april, 2004. specifications and information herein are subject to change without notice.

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